Interview Questions Digital Logic 1.        If inverted output of D flip-flop is connected to its input how the flip-flop behaves? Ø   Clock circuit with frequency divided by 2. 2.        Design a circuit to divide input frequency by 2? Ø   If (clk’event and clk = ‘1’) then output <= not (output); Ø   Positive edge triggered flip-flop with inverted output fed as input. 3.        Design a divide by two counter using D-Latch. Ø   Divided by 2 counter indicates frequency divided by 2 (or) time period multiplied by 2 Ø   If (clk’event and clk = ‘1’) then output <= not (output); 4.        Design a divide-by-3 sequential circuit with 50% duty cycle. Ø   // Posedge counter Ø    always @ (posedge clk_in) Ø    if (reset) begin Ø      pos_cnt <= 0; Ø    end else begin Ø      pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1; Ø    end Ø    // Neg edge counter Ø    always @ (negedge clk_in) Ø    if (reset) begin Ø      neg_cnt <= 0; Ø