VLSI interview questions and answers

Interview Questions

Digital Logic

1.       If inverted output of D flip-flop is connected to its input how the flip-flop behaves?

Ø  Clock circuit with frequency divided by 2.

2.       Design a circuit to divide input frequency by 2?

Ø  If (clk’event and clk = ‘1’) then output <= not (output);

Ø  Positive edge triggered flip-flop with inverted output fed as input.

3.       Design a divide by two counter using D-Latch.

Ø  Divided by 2 counter indicates frequency divided by 2 (or) time period multiplied by 2

Ø  If (clk’event and clk = ‘1’) then output <= not (output);

4.       Design a divide-by-3 sequential circuit with 50% duty cycle.

Ø  // Posedge counter

Ø   always @ (posedge clk_in)

Ø   if (reset) begin

Ø     pos_cnt <= 0;

Ø   end else begin

Ø     pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;

Ø   end

Ø   // Neg edge counter

Ø   always @ (negedge clk_in)

Ø   if (reset) begin

Ø     neg_cnt <= 0;

Ø   end else begin

Ø     neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;

Ø   end

Ø   assign clk_out = ((pos_cnt  != 2) && (neg_cnt  != 2));

5.       What are the different types of adder implementation?

Ø  Ripple carry adder

Ø  Carry select adder

Ø  Carry look ahead adder

6.       Design an OR gate from 2:1 MUX.

 

7.       Design AND gate from 2:1 MUX

 

8.       Design NAND gate from 2:1 MUX

9.       Design NOR gate from 2:1 MUX

10.   Design XOR gate from 2:1 MUX

11.   Design XNOR gate from 2:1 MUX

12.   What is the difference between a LATCH and a FLIP-FLOP?

Ø  Latch is level triggered and Flip-flop is edge triggered.

Ø  Latch can work without a clock where as flip-flop requires clock.

Ø  Flip-flop takes double the resources than latch

Ø  Delay is more for flip-flop (Due to more gates).

Ø  Power consumption of flip-flop is more (Due to more gates).

Ø  Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.

13.   Design a D Flip-Flop from two latches.

14.   Design a 4-bit counter using D Flip-Flop.

It is to be noted that all the flip-flops are negative edge triggered.

15.   Design a 4-bit counter using JK Flip-Flop.

The above counter is a synchronous counter.

16.   Design a 4-bit counter using T Flip-Flop

17.   What are the two types of delays in any digital system?

Ø  Gate delay and Wire delay

o   Gate delay: Delay produced by the logic gate to produce response to the input.

o   Wire delay: Delay produced by the wire between the logic gates.

Ø  Lumped delay and Distributed delay

o   Lumped delay: Delay assigned as a single delay in each module, mostly to the output gate of the module.

o   Distributed delay: Delay assigned to each gate in a module.

Ø  Inertial delay and Transport delay (VHDL only)

o   Inertial delay: Prescribes propagation delay plus some minimum input pulse width.

o   Transport delay: Only propagation delay.

18.   Design a Transparent Latch using a 2:1 Mux

       

19.   Design a 4:1 Mux using 2:1 Mux's

20.   Convert NAND and NOR gate into Inverter in two different ways.

21.   Design a D and T flip flop using 2:1 mux only.

B is treated as clock here; A is treated as input to flip-flop.

22.   Define Clock Skew, Negative Clock Skew, Positive Clock Skew?

Ø  Clock Skew: phenomenon in synchronous circuits in which the clock signal arrives at different components at different times.

Ø  Positive Clock Skew: Positive skew occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register.

Ø  Negative Clock Skew: Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.

23.   What is the difference between an EEPROM and FLASH?

Ø  EEPROM has Byte by Byte erasing facility where as FLASH has sector wise erasing.

24.   What is the difference between a NAND-based Flash and NOR-based Flash?

Ø  Write-time for NAND flash is less than NOR flash.

Ø  Erase-time for NAND flash is less than NOR flash.

Ø  Read-time for NOR-flash is less than NAND flash.

Ø  NAND flash is used for storing large data where NOR flash is used to store small data.

Ø  NAND flash is prone to single-bit errors.

Ø  NAND flash is more dense, less expensive than NOR-flash.

25.   Design a simple circuit based on combinational logic to double the output frequency.

26.  Design a four-input NAND gate using only two-input NAND gates.

 

27.   Why are most interrupts active low?

Ø  If you consider the transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively.

Ø  When it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging. Hence people prefer using active low signals.

28.   How do you detect if two 8-bit signals are same?

Ø  C = A XOR B. If C contains all zeros then A = B else not.

29.   7-bit ring counter's initial state is 0100010. After how many clock cycles will it return to the initial state?

Ø  6 clock cycles

30.    In a 3-bit Johnson's counter what are the unused states?

Ø  2(power n)-2n is the one used to find the unused states in Johnson counter.
So for a 3-bit counter it is 8-6=2.Unused states=2.

Ø  Used States: 000, 100, 110, 111, 011, 001, 000

Ø  Unused States: 010, 101

31.   What is difference between RAM and FIFO?

Ø  FIFO is first in first out, which is usually implemented with Register array.

Ø  RAM is Random access memory.

Ø  Any location of RAM can be accessed at any time. But it’s not the case with FIFO.

Ø  FIFO does not have any address input. But RAM has it.

Ø  FIFO is used for synchronization purpose, where as RAM is used for storage purpose.

32.   What is an LFSR? List a few of its industry applications.

Ø  LFSR- Linear Feedback Shift Register.

Ø  LFSR is a shift register whose input bit is a linear function of its previous state.

Ø  The only linear functions of single bits are xor and inverse-xor; thus it is a shift register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift register value.

Ø  The initial value of the LFSR is called the seed.

Ø  Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences, fast digital counters, and whitening sequences. Both hardware and software implementations of LFSRs are common. 

33.   What is latch up?

Ø  Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on.

Ø  Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS)

34.   Why is NAND gate preferred over NOR gate for fabrication?

Ø  NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes. So compared to NOR, NAND is a faster gate.

Ø  Additionally, the gate-leakage in NAND structures is much lower.

35.   What is Noise Margin?

Ø  The minimum amount of noise that can be allowed on the input stage for which the output will not be affected.

36.   Explain sizing of the inverter?

Ø  In order to drive the desired load capacitance we have to increase the size (width) of the inverters to get an optimized performance.

37.   What happens to delay if we include a resistance at the output of a CMOS circuit?

Ø  Increases. (RC delay)

38.   What is the fundamental difference between a MOSFET and BJT?

Ø  In MOSFET, current flow is either due to electrons (n-channel MOS) or due to holes (p-channel MOS) - In BJT, we see current due to both the carriers. Electrons and holes.

Ø  BJT is a current controlled device and MOSFET is a voltage-controlled device.

39.   Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this?

Ø  Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.

Ø  Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.

Ø  Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability

40.   What is skew, what are problems associated with it and how to minimize it?

Ø  In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.

Ø  This is typically due to two causes.

o   The first is a material flaw, which causes a signal to travel faster or slower than expected.

o   The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times.

Ø  Clock skew can cause harm in two ways.

o   Setup Violation

o   Hold violation

41.   What is slack?

Ø  'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen'.

Ø  Slack = Tdead – Tact

Ø  Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late and a timing violation.

42.   Given only two xor gates one must function as buffer and another as inverter?

Ø  Tie one of xor gates input to 1 it will act as inverter.

Ø  Tie one of xor gates input to 0 it will act as buffer.

43.   Difference between Mealy and Moore state machine?

Ø  Mealy machine has outputs that depend on the present state and inputs.

Ø  Moore machine has outputs that depend on present state only.

Ø  In Moore machine, there is a possibility of glitches appearing in the output variables.

Ø  Mealy machines give you outputs instantly.

44.   How to achieve 180-degree exact phase shift?

Ø  Never tell using inverter.

Ø  DCM an inbuilt resource in most of fpga can be configured to get 180-degree phase shift.

Ø  Bufgds that is differential signaling buffers, which are also inbuilt resource of most of FPGA, can be used.

45.   Tell some of applications of buffer?

Ø  They are used to introduce small delays.

Ø  They are used to eliminate cross talk caused due to inter electrode capacitance due to close routing.

Ø  They are used to support high fan-out, e.g.: bufg

46.   What is Race-around problem? How can you rectify it?

Ø  The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0; this is called the race around problem.

Ø  To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the F-F; this is restrictive so the alternative is master-slave or edge-triggered construction.

47.   N number of XNOR gates are connected in series such that the N inputs (A0, A1, A2...) are given in the following way: A0 & A1 to first XNOR gate and A2 & O/P of First XNOR to second XNOR gate and so on... Nth XNOR gates output is final output. How does this circuit work? Explain in detail?

Ø  If N=Odd, the circuit acts as even parity detector, i.e. the output will 1 if there are even number of 1's in the N input...This could also be called as odd parity generator since with this additional 1 as output the total number of 1's will be ODD.

Ø  If N=Even, just the opposite, it will be Odd parity detector or Even Parity Generator.

48.   Design a circuit that calculates the square of a number? It should not use any multiplier circuits. It should use Multiplexers and other logic?

Ø  This is interesting....
1^2=0+1=1
2^2=1+3=4
3^2=4+5=9
4^2=9+7=16
5^2=16+9=25

Ø  And so on
See a pattern yet? To get the next square, all you have to do is add the next odd number to the previous square that you found.

Ø  Wouldn't this be a possible solution to your question since it only will use a counter, multiplexer and a couple of adders? It seems it would take n clock cycles to calculate square of n.

49.   How will you implement a Full subtractor from a Full adder?

Ø  All the bits of subtrahend should be connected to the xor gate. Other input to the xor being one. The input carry bit to the full adder should be made 1. Then the full adder works like a full subtractor

50.   What is difference between setup and hold time?

Ø  Setup violations are related to two edges of clock, I mean you can vary the clock frequency to correct setup violation.

Ø  But for hold time, you are only concerned with one edge and does not basically depend on clock frequency.

51.   Consider two similar processors, one with a clock skew of 100ps and other with a clock skew of 50ps. which one is likely to have more power? Why?

Ø  Clock skew of 50ps is more likely to have clock power.

Ø  This is because it is likely that low-skew processor has better designed clock tree with more powerful and number of buffers and overheads to make skew better.

52.   What are multi-cycle paths?

Ø  Multi-cycle paths are paths between registers that take more than one clock cycle to become stable.

Ø  Place and Route tools are capable of fixing multi-cycle paths problem.

53.   Implement the following circuits:
(a) 3 input NAND gate using min no of 2 input NAND Gates
(b) 3 input NOR gate using min no of 2 inpur NOR Gates
© 3 input XNOR gate using min no of 2 inpur XNOR Gates
Assuming 3 inputs A,B,C?

3 input NAND:
Connect:
a) A and B to the first NAND gate
b) Output of first Nand gate is given to the two inputs of the second NAND gate (this basically realizes the inverter functionality)
c) Output of second NAND gate is given to the input of the third NAND gate, whose other input is C
((A NAND B) NAND (A NAND B)) NAND C Thus, can be implemented using '3' 2-input NAND gates. I guess this is the minimum number of gates that need to be used.
3 input NOR:
Same as above just interchange NAND with NOR ((A NOR B) NOR (A NOR B)) NOR C
3 input XNOR:
Same as above except the inputs for the second XNOR gate, Output of the first XNOR gate is one of the inputs and connect the second input to ground or logical '0'
((A XNOR B) XNOR 0)) XNOR C

54.   Is it possible to reduce clock skew to zero? Explain your answer?

Ø  Even though there are clock layout strategies (H-tree) that can in theory reduce clock skew to zero by having the same path length from each flip-flop from the pll, process variations in R and C across the chip will cause clock skew as well as a pure H-Tree scheme is not practical

55.   Convert D-FF into divide by 2. (Not latch)? What is the max clock frequency of the circuit, given the following information?
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS
Circuit:
Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2.
Max. Freq of operation:
1/ (propagation delay + setup time) = 1/16ns = 62.5 MHz

56.   How many 2 input xor's are needed to implement 16 input parity generators?

Ø  It is always n-1 where n is number of inputs.

Ø  So 16 input parity generator will require 15 two input xor's

57.   Design a circuit for finding the 9's compliment of a BCD number using 4-bit binary adder and some external logic gates?

Ø  9's compliment is nothing but subtracting the given no from 9.So using a 4 bit binary adder we can just subtract the given binary no from 1001(i.e. 9).

Ø  Here we can use the 2's compliment method addition.

58.   There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of triangle what is probability that they will collide?

Ø  Ants can move only along edges of triangle in either of direction, let's say 1 and another represent one by 0.

Ø  Since there are 3 sides eight combinations are possible, when all ants are going in same direction they won't collide that is 111 or 000.

Ø  So probability of collision is 2/8=1/4

59.   Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?

60.   How to implement a Master Slave flip flop using a 2 to 1 mux?

61.   How to calculate maximum operating frequency?

62.   How to find out longest path?

63.   What is the basic difference between analog and digital design?

64.   What advantages do synchronous counters have over asynchronous counters?

Ø  Since all inputs are synchronized with a common clock, no interrupts can occur in the middle of a state transition for a synchronous counter.

Ø  Asynchronous counters are actually easier to construct, as they usually require less combinational logic.

Ø  In synchronous counters, all flip-flops change simultaneously and in asynchronous counters, the propagation delay of the flip-flops adds up to produce the overall delay.

65.   The combinational element of a counter can be made with...

Ø  Logic Gates, PLA and ROM

66.   What types of flip-flops can be used to implement the memory elements of a counter?

Ø  D, T, JK flip-flops

67.   What are the advantages of using a microprocessor to implement a counter rather than the conventional method (flip-flop and logic gates)?

Ø  A microprocessor is much more flexible.

Ø  A dedicated hardware device, as its name suggests, can only perform the function it was designed to do. A single microprocessor can perform many different functions.

68.   What is the principal advantage of Gray Code over straight (conventional) binary?

Ø  No intermediate states occur during transition.

69.   How many 4:1 mux do you need to design a 8:1 mux?

Ø  2 number of 4:1 mux and one 2:1 mux

70.   What is D-Word, Q-word?

Ø  D-word means double word (32 bits).

Ø  Q-word means Quad word or Quadruple word (64 bits)

71.   Design a 2bit up/down counter with clear using gates. (No verilog or vhdl)

72.   In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

Ø  If the input signal is asynchronous with the clock (state machine clock), then you need to double clock the same signal to synchronize with the state machine clock.

Ø  When signal transfer from one clock domain sequential to another clock domain sequential logic.

73.   How many bit combinations are there in a byte?

Ø  2^8 = 256

74.   What is the difference between latches and flip-flops based designs?

Ø  Latch based design and flop based design is that latch allows time borrowing which a tradition flop does not.

Ø  That makes latch based design more efficient.

Ø  But at the same time, latch based design is more complicated and has more issues in min timing (races).

75.   What is local-skew, global-skew, and useful-skew mean?

Ø  Local skew: The difference between the clock reaching at the launching flop vs the clock reaching the destination flip-flop of a timing-path.

Ø  Global skew: The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.

Ø  Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

76.   What is Boolean algebra? What are truth tables? What are Boolean functions?

Ø  Boolean algebra is the method of representing various Boolean circuits in terms of various functions with variables like x, y and z.

Ø  Truth tables are representation of Boolean functions in graphical format with all the combinations of them.

77.   What is min-term? What is max-term? What is canonical form?

Ø  Min-term are of type abc, ab'c and abc' for a Boolean function of the three variables a, b and c. There are 2^n min-terms of n variables

Ø  Max-term are of type (a+b'+c) and (a'+b+c) for a Boolean function of the three variables a, b and c. There are 2^n max-terms of n variables

Ø  Canonical form is representing the Boolean function in both as a "sum of min-terms" and as a "product of max-terms". This is also known as duality principle.

78.   What are K-Maps?

Ø  K Maps names after their creator Karnaugh are used to reduce the given Boolean expression.

79.   Logic synthesis

Ø  Logic synthesis translates HDL code into connected set of standard cells (called a netlist).

Ø  Technology library is a collection of optimized standard cells with known parameters.

Ø  Architectural-level synthesis:

o   Determine the macroscopic structure:

o   Interconnection of major building blocks.

Ø  Logic-level synthesis:

o   Determine the microscopic structure:

o   Interconnection of logic gates.

Ø  Geometrical-level synthesis:

o   (Physical design): placement and routing

o   Determine positions and connections.

80.   Critical Path

Ø  The longest path from output of registers to input of registers.

Ø  Minimum clock period = Length of critical path.

81.   Optimization methods

Ø  Better architecture like CLA vs. Ripple carry adder.

Ø  Pipelining.

Ø  Parallel processing

Ø  Optimization options of synthesis and implementation tools.

Ø  Reducing fan-out of control signals.

Ø  Better state encoding.

Ø  Registered outputs from state machine.

82.   Logic optimization flow

Ø  Transistor count reduction: Area reduction

Ø  Circuit count reduction: Power reduction

Ø  Gate count (fan-out) reduction: Delay reduction

83.   Design constraints

Ø  Timing, Area and Power

84.   Faster designs are big. Why?

Ø  The design has to be paralleled for better timing and hence more area.

85.   FPGA design flow

86.   XST synthesis overview

Ø  XST input files

o   VHDL IEEE 1076-1987

o   Verilog IEEE 1364-1995 and IEEE 1364-2001

o   XCF

§  Xilinx constraints file in which you can specify synthesis, timing and specific implementation constraints that can be propagated to the NGC file.

o   UCF

§  User constraints file contains the constraints specified by the user.

§  Contains timing, placement and pin out constraints.

o   NCF

§  Netlist constraints file defines constraints for schematic editors and third party tools

o   Core files

§  These files can be in either EDIF or NGC format.

§  EDIF is the electronic data interchange format file, an industry standard file format for specifying design netlist.

§  XST does not modify cores.

§  It uses them to inform area and timing optimization.

§  Cores are supported for FPGA only, not CPLD.

Ø  XST output files

o   Synthesis report. (.txt)

§  Contains area and timing estimation.

o   RTL Schematic (.ngr)

§  Schematic representation of pre-optimized design shown at the register transfer level.

§  Contains generic symbols such as adders, gates, counters, multipliers etc.

§  It is generated before optimization of the design.

o   Technology Schematic (.ngc)

§  Schematic representation of NGC file shown in terms of logic elements optimized to the target architecture.

§  Contains LUT, carry logic, I/O buffers etc.

§  It is generated after optimization phase of synthesis process of the design

§  NGC file contains both logical data and constraints.

87.   What is a false path?

Ø  False path is a path, which physically exists but logically never executed.

Hardware

1.   Which one you prefer RAM or a Regfile? Why?

Ø  RAM is used for low power and low area.

Ø  REGFILE is used for Better timing.

2.   A timing path fails: what are your options?

Ø  Look for parallelism in RTL.

Ø  Look for small RAMs which might be synthesized

Ø  Look for better placement

Ø  Look for Pipelining opportunity

Ø  Look for moving logic before the Reg

Ø  Look for replicating the drivers to reduce load if the delay is caused by loading

Ø  Use One Hot instead of Binary coded State Registers

3.   What will happen if you don’t include a signal in the sensitivity list and use/read it inside the process?

Ø  By default, every signal entering the combinational logic should be listed in the sensitivity list.

Ø  If you do not respect this, you can have mismatches between simulation and synthesis.

Ø  Depending on context, sometimes XST will create a latch, and sometimes it will assume you intended to include the signal in the sensitivity list.

Ø  If a signal that is an input to a process is not in the sensitivity list of the RTL code then there may be differences between the two simulations.

Ø  The logic that is implemented by the synthesis tool has to be based on all inputs.

4.   GUIDELINES FOR IMPROVING PERFORMANCE OF SYNTHESIS

Ø  Clock and Reset logic

o   Clock and Reset generation logic for the modules should be kept in one module.

o   Synthesis only once and do not touch. This helps in clean clock constraints specifications.

o   Another advantage is, the modules that are using these clocks and resets can be constrained using the ideal clock specification.

Ø  No glue logic at the top

o   The top module should be used only for connecting various components (modules) together. It should not contain any glue logic.

Ø  FSM Coding

o   While coding FSMs, the state names should be described using the enumerated types.

o   The combinational logic for computing the next state should be in its own process, separate from the state registers.

o   Implement the next-state combinational logic with a case statement. This helps in optimizing the logic much better and results in a clean design.

Ø  Multiplexer Inference

o   A case statement is used for implementing multiplexers. To prevent latch inferences in case statements, the default part of the case statement should always be specified.

Ø  Tri-state buffers

o   A tri-state buffer is inferred when a high impedance (Z) is assigned to an output.

o   Tri-state logic is generally not always recommended because it reduces testability and is difficult to optimize, since it cannot be buffered.

Verilog

1.   What is the difference between a Verilog task and a Verilog function?

Ø  A function shall execute in one simulation time unit. A task can contain time-controlling statements.

Ø  A function cannot enable a task. A task can enable other tasks or functions.

Ø  A function shall have at least one input type argument and shall not have an output or inout type argument. A task can have zero or more arguments of any type.

Ø  A function shall return a single value. A task shall not return a value.

2.   Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin

   a  = 0;

   a <= 1;

   $display(a);

end       

Ø  This is a tricky one!  Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

   1: Active Events                (blocking statements)

   2: Inactive Events              (#0 delays, etc)

   3: Non-Blocking Assign Updates  (non-blocking statements)

   4: Monitor Events               ($display, $monitor, etc).

Ø  Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue.

Ø  Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0.  If we were to look at the value of a in the next sim cycle, it would show 1.

3.   What is the difference between the following two lines of Verilog code?

#5 a = b;

a = #5 b;

Ø  #5 a = b; Wait five time units before doing the action for "a = b;". The value assigned to a will be the value of b 5 time units hence.

Ø  a = #5 b;  The value of b is calculated and stored in an internal temp register. After five time units, assign this stored value to a.

4.   What is the difference between?

c = foo ? a : b;

and

if (foo) c = a;

else c = b;

Ø  The? Merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x.

Ø  On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

5.   Verilog coding guidelines

Ø  Guideline #1: When modeling sequential logic, use non-blocking assignments.

Ø  Guideline #2: When modeling latches, use non-blocking assignments.

Ø  Guideline #3: When modeling combinational logic with an always block, use blocking assignments.

Ø  Guideline #4: When modeling both sequential and combinational logic within the same always block, use non-blocking assignments.

Ø  Guideline #5: Do not mix blocking and non-blocking assignments in the same always block.

Ø  Guideline #6: Do not make assignments to the same variable from more than one always block.

Ø  Guideline #7: Do not make assignments using #0 delays.

·         Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth,

   A synchronized fifo

• Writing clock 30MHz - F1
• Reading clock 40MHz - F2
• Writing Burst Size - B
• Case 1 : There is 1 idle clock cycle for reading side - I
• Case 2 : There is 10 idle clock cycle for reading side - I

    FIFO depth calculation = B - B *F2/(F1*I)

   

If if we have alternate read cycles i.e between two read cycle there is IDLE cycle.

FIFO depth calculation = B - B * F2/(F1*2)

In our present problem FIFO depth = B - B *40/(30*2)= B(1-2/3)= B/3

That means if our Burst amount of data is 10 , FIFO

DEPTH = 10/3 = 3.333 = 4 (approximatly)

 if B = 20 FIFO depth = 20/3 = 6.6 = 7or 8 (clocks are asynchronous)

   

If B = 30 FIFO depth = 30/3 = 10

10+1 = 11 (clocks are asynchronous)

If 10 IDLE cycles between two read cycles .

FIFO DEPTH = B - B *F2/(F1*10) .

= B(1-4/30)

= B * 26 /30