Sanity checks before floorplan in Physical design

Sanity checks before floorplan in Physical design

Sanity checks are an important step for physical design engineers to make sure that the inputs received for physical design are correct and consistent. Any issues in the input may cause problems in the later stages. So it is important to perform the sanity checks in the initial stage that is when the design is loaded in PnR tool and before the start of the floorplan.

Here is a list of checks which must be performed before floorplan of design.

Figure-1: Sanity checks before floorplan

Library Check:

In library check, basically, we validate the libraries before starting the physical design by checking the consistency between the physical and logical library.  It also checks the quality of both libraries and reports the error if any. The cells used in the design must be present in the logical as well as in the physical library.

Innovus commands:

check_design -physicalLibrary : This command will check the physical library and report that all the cells used in design have their LEF view or not.

check_design -timigLibrary : This command will check the timing library and report that all the cells used in design have defined in timing library or not.

check_design -all : This command will check the missing or inconsistent library and design data.

ICC command:

check_library : Performs consistency checks between the logical and physical library, across the logical library and within the physical library.

Netlist Check:

Netlist must be checked for consistency. This check analyzes the current loaded netlist and reports the inconsistency if any. Netlist check mainly checks:

1. Floating input pins and nets
2. No direct connection between VDD and VSS
3. Multidriven nets
4. combinational loops
5. Unloaded outputs
6. Uncontraints pins
7. Mismatch pin count between instance and reference

Innovus command:

check_design -netlist

ICC command:

check_design

SDC Check:

SDC file must be checked before start the design. Some of the common issues in SDC file are as follow.

1. Unconstrained path
2. Clock is reaching to all synchronous elements
3. Multiclock driven registers
4. Unconstrained endpoint
5. Input/output delay missing for a port
6. Slew or load constraint missing for a port
7. Missing clock definition

Innovus command:

check_timing

ICC command:

check_timing

Thank you.