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Float gate inputs may pickup any value. So

1.Both the transistors may form the conduction path and short circuit VDD&VSS. Power dissipation increases.

2.ESD signals directly enter the gate and destroy the gate oxide.

3.Inputs may pick up the unnecessary signals from the by side nets and destroy the functionality of the down the stage circuits.

4.To avoid these problems we connect the spare gate inputs either to 1/0.

Floating output's

Connected to the drain & source and is not a problem to the device structure.

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