Physical Verification Basics Part 1

Physical verification is a process of verifying layout data against fabrication specific rules

Inputs

1.GDSII(layout ) file

2 Verilog netlist

3 Rule deck (fabrication rules) file

Checks

1.LVS

2 DRC

3 Antenna

4 Density

5 drc_SK

LVS (layout vs schematic)

Tool generates layout netlist & schematic netlist, compares verilog & schematic netlist, if they match lvs gets pass, if they didn't match, lvs will fail

Inputs for LVS

1) GDSII

2) Verilog netlist

LVS checks are of two types

1) Icc lvs

2) icv lvs (trc lvs)

Types of lvs errors

1) Opens

2) Shorts

3) Component mismatch

4) Parameter mismatch

Opens:

When same net is left unconnected, it results open

Causes

1) via missing

2) if a net is not connected to it's respective pin

3) break in net

Fix

Need to route the signal

Shorts:

When two different signals overlaps with each other, it will results a short

We may classifiy into 3 types by nature of the signal

Signal short.

Clock short

Power short

Fix :

Need to do rerouting

ICV LVS:

When two signals overlaps each other with the help of fill, it causes a trc short

Component mismatch:

Instead of placing one type of device, if it's places other type of device

Example : Instead of placing nmos, if we place pmos device it will falls in the category of component mismatch error

Parameter mismatch:

If there is any change in w/l values while compared with both netlists, it will results in parameter mismatch error

Bind keys(icc2)

Ctrl+ shift +N - to get complete net

Ctrl + shift +P - to get pins for a selected net

Ctrl + H - to highlight.

Ctrl +U - ruler (scale)

Shift + L- chop/split

Ctrl + shift + M - to Dehilight the selected

C - copy

D - delete

M - move

Shift + H - to route with out via

Shift + R - to route with via.

Shift + W - to move net with vias

Ctrl + R - Properties

Ctrl + B - Select by name

Comments

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