Why we are not checking the hold before CTS? Ans: Before CTS, clock is ideal that means exact skew is not there. All the clocks reaching the flops at the same Time. So, we dont have skew and transition numbers of the clock path, but this information is sufficient to perform setup analysis since setup violation depends on the data path delay. Clock is propagted only after CTS (actual clock tree is built, clock buffers are added & clock tree hierarchy, clock skew, insertion delay comes into picture) and that's why hold violations are fixed only after CTS.
It would be helpful if you add related tool commands. So someone can try realtime.
ReplyDeleteSure
DeleteHow to get note book or pdf
ReplyDeleteHello Praveen, You are doing a great job by sharing your knowledge....
ReplyDeleteI have a doubt regarding shielding
* Can we place VDD net to shield the aggressor net instead of VSS
(If your answer is Yes/No. Please explain)
Yes Jagruth, we can do with VDD as well, as it will be driven by a stable dc source
Deleteand reduicng the cross talk between the clock net and sig1/sig2 net.
Very informative blog...
ReplyDelete